1. Field of the Invention
This invention relates in general to a semiconductor memory device and, more particularly, to a semiconductor memory device having a redundant circuit containing spare memory cells available for exchanging the same in place of a defective memory cell or cells. This invention has particular applicability to a static semiconductor memory device.
2. Description of the Background Art
FIG. 5 is a block diagram showing an example of a conventional static semiconductor memory device having a redundant circuit.
Referring to FIG. 5, the semiconductor memory device includes an array of memory cells 7 including a spare column cell 71S, an address buffer 61 for receiving external address signals and outputting internal address signals A.sub.0 to A.sub.n, a row decoder 6 and a column decoder 8 for receiving these input internal address signals and outputting signals for designating specified memory cells, a sense amplifier 9 for amplifying signals from the array of memory cells 7, a fuse circuit 62 for putting a column containing a defective memory cell or cells out of use, and a defective cell programming circuit 67 for programming a column containing the defective memory cell or cells.
The column decoder 8 includes a spare column decoder 8S connected to the spare column cell 71S. The sense amplifier 9 includes a spare sense amplifier 9S for amplifying signals from the spare column cell 71S. Input data Di are supplied via an input buffer 63 to the array of memory cells 7. The signals read out from the sense amplifier 9 are outputted via a read data bus 5 and an output buffer 64 as the output data Do.
FIG. 6 is a circuit diagram showing a portion of the semiconductor memory device shown in FIG. 5 corresponding to the redundant circuit.
Referring to FIG. 6, the internal address signals A0 to Am are supplied to the row decoder 6, while the remaining internal address signals Am+1 to An are supplied to the column decoder 8. The row decoder 6 and the column decoder 8 include a NAND gate and an inverter for each address signal. The defective cell programming circuit 67 is connected for receiving the internal address signals Am+1 to Am, and has its output connected to a NAND gate 81 (spare decoder) for determining that the spare column cell in the column decoder 8 is to be used. An enabling circuit 82 for enabling the NAND gate 81 is connected to one input of the NAND gate 81. The enabling circuit 82 includes an enabling fuse F.sub.1 which, when blown off, enables the NAND gate 81 to enable all of the redundant circuit.
The column decoder 8 has its output connected to each column of the array of memory of cells 1 via fuse circuit 62, excluding the spare column cell. The fuse circuit 62 has a fuse associated with each column. The defective cell programming circuit 67 includes an address switching circuit AC for programming the addresses of the defective memory cells.
FIG. 7 is a circuit diagram showing an example of the address switching circuit.
This address switching circuit AC includes a fuse FS2 for programming the addresses for the defective memory cells. When an input signal X is supplied to the circuit, a non-inverted output signal X is outputted if the fuse is not blown off, and an inverted output signal X is outputted if the fuse FS2 is blown off.
The operation of the circuit shown in FIG. 6 is explained.
When no defective memory cell or cells are present, the spare column cell 71S is not used. At this time, the defective cell programming circuit 67, fuse circuit 62 and the enabling circuit 82 are not in operation. Hence, a spare transfer gate is not opened. In this case, usual accessing is performed without employing these redundant circuits.
When a defective memory cell or cells exists, the spare column cell 71S comes into use. To this end, the following preparatory operation is necessitated. First, the enabling fuse Fl of the enabling circuit 82 is blown off. This enables the NAND gate 81 to enable the redundant circuit. Then, in the fuse circuit 62, that fuse which is connected to the column where the defective memory cell or cells exist is blown. The fuse in the address switching circuit AC included in the defective cell programming circuit 67 is also blown off for programming the address where the defective memory cell exist.
When a column containing a defective memory cell or cells is selected by the column decoder 8 by the above described three kinds of fuse blow-off operations, the spare column cell 71S is accessed in place of the column containing the defective memory cell.
FIG. 8 is a circuit diagram showing the redundant circuits in cases wherein the semiconductor memory device has spare row cells.
Referring to FIG. 8, the semiconductor memory includes a spare row cell 72S. A row decoder 6b includes a NAND gate 161 (spare decoder) to which is connected a defective cell programming circuit 68 including address switching circuits AC as in the case of the circuit shown in FIG. 6. An enabling circuit 82 is connected to one input terminal of NAND gate 161. The output signal of the NAND gate 161 is supplied to the input of each of the other NAND gates of the row decoder 6b. Thus, the semiconductor memory device of FIG. 8 is not in need of the fuse circuit 62 such as shown in FIG. 6.
The operation of the circuit shown in FIG. 8 is explained below.
When defective memory cells are not present, the spare row cell 72S is not used. At this time, neither defective cell programming circuit 68 nor the enabling circuit 82 is in operation, so that accessing is performed as though these redundant circuits were not provided.
When a defective memory cell exists, the spare row cell 72S is used. First, the enabling fuse F1 of the enabling circuit 82 is blown off. This enables the NAND gate 161 to enable the redundant circuits. Then, the fuse of the address switching circuit AC in the defective cell programming circuit 68 is blown off for programming the address for the defective memory cells.
When a row including defective memory cells is selected by the melting of the above described two kinds of fuses, the spare row cell 72S is accessed in place of this row.
A prior-art example having particular pertinence to the present invention is seen in the Japanese Patent Publication No. 31038/1985, which is shown herein FIG. 9.
FIG. 9 is a circuit diagram showing a dynamic semiconductor memory device having redundant circuits.
Referring to FIG. 9, the semiconductor memory shown therein includes a spare row cell constituted by a static memory cell SM. This prior-art example is similar to that shown in FIG. 8 in that, when a defective memory cell or cells exists, a spare row cell is accessed in place of the row including these defective cells. However, since the spare row cell of the prior-art example of FIG. 9 is constituted by the static memory cell SM, no sense amplifier is necessitated, so that it is possible to prevent the delay from being caused by the sense amplifier.
Further prior-art examples having pertinence to the present invention may be seen in the Japanese Patent Laying Open Gazette Nos. 32633-1978, 84634-1978 and 61933-1977. These prior-art examples refer to redundant circuits wherein a column or a row including a defective memory cell or cells is substituted or exchanged in its entirety, as shown in FIGS. 6 or 8.
In addition, the Japanese Patent Laying-Open Gazette No. 151895/1985 discloses a redundant memory cell having a capacity larger than that of the remaining memory cells.
The above described conventional semiconductor memory devices present disadvantages, in the following respects.
First, when the spare column cell 71S is employed, it becomes necessary to employ the fuse circuit 62. This fuse circuit 62 includes a large number of fuses connected for each column. With the progress in the integration of the semiconductor memories, the increasingly narrow fuse pitch gives rise to higher density of the semiconductor memory devices. In the example shown in FIG. 6, it is extremely difficult for the presently employed laser blowing device to melt the fuse having the narrow fuse pitch.
In the examples shown in FIGS. 6, 8 and 9, since the spare column cell 71S or the spare row cell 72S are provided in the array of memory cell 1, the masking pattern may be complicated to present a further disadvantages.
Also, in the examples shown in FIGS. 6, 8 and 9, since the internal address signals are supplied via the address switching circuit AC to the column decoder or the row decoder, the delay in accessing to the semiconductor memory may be caused by this switching circuit AC.
In addition, as shown in FIG. 8, the delay in accessing may be caused by the output signals of the NAND gate 161 being supplied to the inputs of the other NAND gates within the row decoder 6b. That is, when the spare row cell 72S is selected, the NAND gate 161 outputs a signal inhibiting the use of the row including the defective memory cell or cells. This inhibit signal is supplied to the inputs of the other NAND gates within the row decoder 6b. Hence, a further delay in accessing is caused by the prolonged route of transmission of this inhibit signal.
Also, when there is a defective portion in a semiconductor memory device, it frequently occurs that the defective portion exists in a memory cell in only one or a few bits thereof. Thus, in the examples shown in FIGS. 6 and 8, it is wasteful to replace the column or the row in its entirety by the redundant memory cell.
Also, in the conventional mask ROM, since the fuses for programming are larger in size than those in the memory cell, it is impossible to make use of the redundant circuits.